This invention relates to an array configuration for nonvolatile memories of the floating-gate type, such as Flash Electrically-erasable, Programmable Read-Only-Memory (Flash EPROM) arrays. In particular, this invention relates to memory arrays with cells having two stacked conducting layers (stacks), commonly phosphorous-doped polycrystalline silicon (polysilicon or poly) layers. The upper conducting layer forms wordlines and control gates. The lower conducting layer forms floating gates that are located under the control gates. The term "stack", as used herein, includes either a single-layer workline conductor or the combination of the wordline conductor and the underlying conductor.
One such nonvolatile memory array has diffused horizontal source lines formed between pairs of horizontally-directed stacks. The horizontal source lines are connected to metal vertical source lines. The metal vertical source lines are located between groups of columns of cells, each group having perhaps sixteen columns of cells. In many flash EEPROM devices of the foregoing type, the conventional way of connecting the diffused horizontal source lines to the metal vertical source lines is to form a contact at each intersection of such lines. Because of minimal photolithographic dimensions, in prior-art structures the stacks on either side of each source contact are bent in a manner that allows more room for the contact structure, including insulator space and including masking tolerances, to the diffused horizontal source line. The bend in the stacks results in a need for an area with a relatively large horizontal distance for formation the vertical source line. That distance is greater than the horizontal distance needed for each column of cells. As a result, the horizontal spacing between field oxide regions is non-uniform, being wider at the location of the vertical source lines than the horizontal spacing in the groups of columns of cells. Because the spacing between field oxide is non-uniform, the field oxide regions adjacent the vertical source lines tend to be distorted in comparison to the field oxide regions between the grouped columns. In some cases, the distortion is sufficient that dummy columns of cells are used on each side of the metal vertical source line, resulting in an even greater area of non-functional structure on the chip.
These source contacts, and the metal vertical source line connected to those contacts, are needed because the regions under the stack are non-conductive.
The diffused sources, and the diffused horizontal source lines, of Flash EPROMs of the type discussed here are formed from both arsenic and phosphorous implants. When subjected to a drive step at relatively high temperatures, the implanted phosphorous forms a diffused region that extends a short distance under the stack. This short extension, or underlap, under the lower-level floating gate of the stack, is used for flash erasure of the floating gates by Fowler-Nordheim tunneling.
As the minimum photolithographic distances become smaller, the extension of the diffused phosphorous region under the stack forms a greater percentage of the width of the floating gate.
There is a great and continuing need to build smaller memory cells and, therefore, more memory cells on silicon substrate. There is also a great and continuing need for memory-cell layouts that are not only small, but are easy to manufacture as well as easy to shrink in size as minimum photolithographic distances decrease.